This invention related to Graph Based Analysis (GBA) Advanced On Chip Variation (AOCV) Timing Correlation to Path Based Analysis (PBA) Timing and AOCV Comprehension during layout optimization. This invention reduces GBA AOCV Timing Pessimism and improves Performance, Power-Active, Power-Leakage and Area (PPPA) performance.
Synchronous digital circuits are designed for operation at specific clock frequencies. The goals of synthesis and place and route (PnR) optimizations is to realize this frequency of operation in real design layout. Timing closure is the effort expended towards meeting the frequency of operation goals of the design/circuit during the layout. Timing closure involves place and route iterations along with timing analysis of the design including static timing analysis (STA) of the design. Static timing analysis is the verification/checking part of the flow. Place and Route iterations form the implementation flow.
Place and Route tools employ timing driven algorithms to ensure frequency goals are met. The accuracy of the timing analysis is limited using the typically employed graph based analysis method. The signoff STA tools/flows employ path based analysis methods for timing path analysis. These will be described below.
Both PnR tools and STA tools, use the following inputs in timing analysis. The Netlist is a design representation consisting of connections of standard cells and macros such as, etc. Parasitics are the RC-network (resistance/capacitance) representation of the connecting wires. Timing models represent the timing delay of standard cells, memory models, etc. User constraints include: the clock frequency definitions and other timing checks; margins which are additional subtractive components modeling variations due to phase locked loop (PLL) clock source; and derates which are additional slow-down multipliers for modeling on-chip variations like dynamic voltage fluctuations, transistor random variations, etc. These derates may be in the form of AOCV derates. Based on these inputs, the STA tools check the design timing status versus the timing goals which are dependent upon the user specified frequency of operation.
This invention is specific to the AOCV derate usage in PnR flows. Derates work as follows. If the cell delay, based on the context of the cell usage, inputs transition and the output load for the cell, recalled up a timing model table is S and the derate is D then: the non-derated STA delay is S; the derate applied is D; and the derated STA delay of the cell is S*D. For frequency checks, D is usually greater than 1.0 and generally between 1.0 and 1.5. Thus the derate slows down the cell and makes it harder to meet the frequency goals. Derates can be global where every cell in the design gets the same multiplier or context dependent. Context dependent derate is known as AOCV derate.
Context dependent AOCV derates are a function of depth of a cell in the path. FIGS. 1, 2 and 3 illustrate various circuit depths. FIG. 1 illustrates a path depth of 5. The circuit path 100 includes cell F1 101, cell C1 102, cell C2 103, cell C3 104, cell C4 105 and check point cell F2 110 which does not participate in the delay calculation. Thus the path depth of circuit 100 is 5. FIG. 2 illustrates a path depth of 7. The circuit path 100 includes cell F1 201, cell C1 202, cell C2 203, cell C3 204, cell C4 305, cell C4 206, cell C6 207 and check point cell F2 110 which does not participate in the delay calculation. Thus the path depth of circuit 200 is 7.
FIG. 3 illustrates calculation of path depth in a branching path. FIG. 3 illustrates a main path including cell F1 301, cell C1 302, cell C2 303, cell C3 304, cell C4 305, cell C4 306, cell C6 307 and check point cell F2 310 which does not participate in the delay calculation. A first branch path includes cell F1 and first branch check point cell BF1. A second branch includes cell F1, cell C1 302 and second branch check point cell BF2. A third branch includes cell F1 301, cell C1 302, cell C2 303, cell C3 304, cell C4 305, cell C4 306, cell C6 307, branch cell BC1 341, branch cell BC2 342, branch cell BC3 343 and third check point cell BF3. The various paths for each cell are shown in Table 1.
TABLE 1F1C1C2C3C4C4C6Shortest path Depth1277777Longest path Depth10101010101010Actual path Depth7777777
For the circuit illustrated in FIG. 3 the relevant path being tested for speed is cell F1 301, cell C1 302, cell C2 303, cell C3 304, cell C4 305, cell C4 306, cell C6 307 and check point cell F2 310. A Graph Based Analysis (GBA) delay calculation assumes derates corresponding to the SHORTEST depth of a cell. A Path Based Analysis (PBA) analysis considers a depth of the path for derate lookup in the AOCV table. If the derates for depth i is Di then the GBA Path Delay is:F1*D1+C1*D2+C3*D7+C4*D7+C5*D7+C6*D7, andthe PBA Path Delay is:F1*D7+C1*D7+C3*D7+C4*D7+C5*D7+C6*D7.The difference between very low depth derates and very high depth derates can be high. Derates D1 and D2 may be as high as 1.4, while the derate D30 may be 1.05. Thus GBA analysis may be extremely pessimistic and lead to waste of time and resources solving the wrong problem. Generally the derates D1>D2>D3 . . . Dn>Dn+1. Thus the derate gets lower as the path depth increases.
FIG. 4 illustrates a prior art AOCV table. In the prior art table illustrated in FIG. 4, each depth 101 to 103 . . . 111 to 112 . . . 120 is matched with a corresponding derate value 131 to 133 . . . 141 to 142 . . . 150. In accordance with the prior art each derate value 131 to 133 . . . 141 to 142 . . . 150 is unique.